TimeQuest with Stratix III to Stratix III I/F

Thanks for taking a look at this.

In this case the clock fans out to the 3 FPGA's, I've started out using this scheme to transfer data between the boards but I also have the option of going source synchronous.

For now I would like to understand the basic approach with the clock fanned out to the three parts. I have been reading AN433 which appears to have some useful information even though it is written for source synchronous.

I've also noticed that the tco for the second FPGA are affected by meeting the setup and hold times for data from the first FPGA, much slower which in turn affects the timing in IC3. This makes me think I can't implement this without phase shifting the input and output clocks independently of the board clock and resyncing to the board clock in each device. Considering that source synchronous may be more desirable.