TimeQuest with Stratix III to Stratix III I/F

How does your clock feed the three devices? Is it a board clock fanning out to all three, or running chip to chip with the data(source-synchronous)?

Note that there is some "chicken and the egg" when it comes to I/O timing between FPGAs, since both devices have variance to meet timing. If timing is tight, you have to figure out what the best one side can do and then apply that to the other FPGA. If it's loose, just take your 10ns clock period, take out your board delay, and give half of that to each side to work with. If one doesn't make timing, start tweaking.