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Merging altshift_taps doesn't require any more ports no matter how many you merge. At the basic level, altshift_taps is a memory with a free-running read and write counter offset by the shift register length. So let's say a shift register is 8 bits wide and 40 bits long. The write pointer would start at 40, the read pointer at 0, and they would just go. (I think the offset is a little less than 40 to account for latency, but that's the basic idea). All reads and writes are 8 bits. Now let's merge it with another shift register that is 8-bits wide and 40 long. No extra ports are needed, just the memory width is increased to 16, with half the inputs/outputs making up one shift register and the other half making up the other. But still only one read pointer and one write pointer.
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OK so basically what you are saying is expand the memory width rather than use extra ports. Leads me back to my original problem of how does TimeQuest report routes between dividers, if the buses are segmented as you describe then there would be no routeing for this share as different RAM bits would go to different dividers.
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