--- Quote Start ---
alt_shift_taps is a shift register built out of RAM. Quartus synthesis can merge multiple shift registers that are the same length and same clock domain, into a single altshift_taps. The problem is that the memory can only have one logical name, so it gets the name of one of the shift registers. I'm not sure if that's what's occuring, but could be it.
a) Assignments -> Settings -> Analysis & Synthesis -> More Settings -> Allow Shift Register Merging Across Hierarchies = Off.
This is a relatively new setting, and before it was available, another workaround I've previously used is:
b) Create a partition on one(or both) of the hierarchies. Since there is no synthesis across hierarchies, it stops that from occurring.
If this isn't it, there's a decent change item b) will fix it anyway.
(The other one to turn off is under the same menu but More Settings -> Remove Duplicate Registers. Registers with the same behavior can get merged across hierarchies. I often recommend turning this off regardless, especially a high-speed desigin. You might get something silly like a toggle register that gets merged across multiple hierarchies, and now it pulls them all in together. My assumption is its the altshift_tap based on the name though...)
--- Quote End ---
Sounds like a good possibility, looking in the Project Navigator only one of the 6 dividers uses a RAM block (863 bits in 9 x M9Ks) so it is possible that the rest is shared between the other dividers, presumably for the pipe-lining. I'll try the assignment setting, thanks. Doesn't the limit of 2 read/write ports on an M9K limit the sharing to two modules though?
Honored Contributor
