Timequest constraints for a dynamically phase-shifted PLL

I think you are still missing the point. Let's just analyse what you have got.

1. You have a reference clock (50 MHz) and a derived/generated PLL clock (300 MHz) with adjustable phase.

2. At one or perhaps more of the phase settings you get inconsistent results which you describe as metastability.

3. At those phase settings, it is quite possible that the transfer of data from the 50 MHz clock edge to a 300 MHz clock edge (not necessarily the closest edge) may result in inconsistency/uncertainty/metastability because the setup and/or hold times for that transfer are not being met.

4. Applying multicycle constraints to this will not alter anything other than make it look like you are meeting timing when in reality you are not.

I don't think I can put it in clearer terms than this.