Timequest constraints for a dynamically phase-shifted PLL

Hi,

I think you are providing to little info about your project to attract gurus :) maybe draw some basic block diagram from which clocks and PLLs can be seen. In addition Can you post your .sdc file? As from my experience I would do like:

1. Constrain all base clocks.

2. Constrain generated clocks with correct properties frequency phase shift, use -add Argument if there is more than one clock. Check TimeQuest "Clock" and "Clock Tree" reports to see if all you clock constrains are correct.

3. Use set_clock_groups with -logically_exclusive Argument to cut clock transfers between PLL phase shifted clocks. Check TimeQuest "Clock Transfers" report to see if detected clock transfers are correct.

4. Check setup and hold reports for every phase shifted clock, check that you have proper launch and latch clock edge relationship.

5. set_multicycle_path if they are necessary.

6. Check if any constrains are ignored.

That should be enough to constrain dynamically phase shifted PLL clocks (I am assuming you allready done that).

As I understand you have some timing related issues when running on hardware but TimeQuest reports say that there are no timing errors in all corners? Maybe you have added some false path exceptions where you should not?