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Altera_Forum's avatar
Altera_Forum
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17 years ago

Timequest and PLL jitter

Hi, is it necessary to specify any timing jitter when using PLL outputs in an SDC file i.e. as well as the derive_pll_clocks command? Is there anything else I need to do to make sure I'm covering...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

My advice is that you concentrate on your hold timing. Make sure your hold constraints are ok (e.g. you didn't accidentally false path or multicycle a path you did not intent to). Use the check_timing and report_timing functionality to help you out. Also put special attention to your I/O timing, another area people tend to make mistakes when constraining.

It is hold timing, by the way, the main reason you should not pad your timing. Padding may help you with setup timing, but will hurt your hold.

And yes, definitely use derive_clock_uncertainty.