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Altera_Forum
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17 years ago

Timequest and PLL jitter

Hi, is it necessary to specify any timing jitter when using PLL outputs in an SDC file i.e. as well as the derive_pll_clocks command? Is there anything else I need to do to make sure I'm covering...
Altera_Forum's avatar
Altera_Forum
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17 years ago

No, they concur with my thoughts really. As far as I'm concerned, my job is to ensure the functionality/logic is correct and to specify the timing requirements as they are to Quartus. From there on, the tools should do the rest. So, I'm not going to add any false padding. I will add the clock uncertainty though as I think this is perfectly valid (and recommended by Altera).

And, yes, there is still a suspicion that I've got something wrong in the logic - I'm currently double checking my simulation testbench.

Thanks for everything.