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Altera_Forum
Honored Contributor
Honored ContributorTimequest and PLL jitter
Hi, is it necessary to specify any timing jitter when using PLL outputs in an SDC file i.e. as well as the derive_pll_clocks command? Is there anything else I need to do to make sure I'm covering...
Altera_ForumHonored Contributor
Honored ContributorThanks for your help, I really appreciate it.
So, as a first pass I will add the derive_clock_uncertainty clause to my sdc file. At leat I will then know if I'm way out. The lower end of my setup slack distribution curve is quite low (100pS or thereabouts), so yes I could try setting a minium slack constraint. I'm not so sure what margin I should use though, until now I have assumed that any value of positive slack is OK given that I'm checking all 3 v-t points. I do take the point about SignaTap. I do use it when I hit problems and it has proven to be extremely useful.
