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Altera_Forum's avatar
Altera_Forum
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17 years ago

Timequest and PLL jitter

Hi, is it necessary to specify any timing jitter when using PLL outputs in an SDC file i.e. as well as the derive_pll_clocks command? Is there anything else I need to do to make sure I'm covering...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

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I'm getting some wierd results on Stratix III even though my timing analysis is reporting positive setup and hold slack. I've done what I believe to be a pretty thorough job of specifying the timing constraints but I'm beginning to wonder if I've missed anything.

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Even though you were careful, review these reports if you haven't already:

  • Report Ignored Constraints

  • Report Unconstrained Paths

  • Check Timing

  • Design Assistant