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is it necessary to specify any timing jitter when using PLL outputs in an SDC file i.e. as well as the derive_pll_clocks command? Is there anything else I need to do to make sure I'm covering myself timing wise?
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derive_clock_uncertainty accounts for PLL jitter. This command is required for 65 nm (like Stratix III) and newer device families. In QII 8.1 you get a warning for those families if you don't use clock uncertainty and an Info message if you manually add less uncertainty than would be added by this command.
From the derive_clock_uncertainty on-line help page:
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This command auto-generates a file named PLLJ_PLLSPE_INFO.txt... that lists the names of the PLLs in the design as well as their jitter and SPE values.
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Do constraints attached to the external clock input have an impact on PLL clocks? I have not specified jitter on the external clock inut and wonder if this may be a problem.
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Some configurations of PLLs let the input jitter pass through to the output. The Stratix III device handbook says, "A high-bandwidth PLL provides a fast lock time and tracks jitter on the reference clock source, passing it through to the PLL output." I filed a service request asking how this case is handled with derive_clock_uncertainty. I was told that derive_clock_uncertainty gives an uncertainty based on the maximum possible output jitter for the maximum allowed input jitter for PLL configurations that let the input jitter pass through the PLL. You don't need to add clock uncertainty manually to the device input pin driving the PLL if that pin is used only by the PLL. I didn't ask about the case where that input pin also clocks registers directly, but you can check the TimeQuest report to see whether derive_clock_uncertainty is creating uncertainty for that case.
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