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allright, I have to change the design. I see the point. Basically all the registers have to physically stop operation (using clkenable) and it is not enough to slow the data stream.... that of course has some consequencies in latency. if my SQRT has latency of 4 clock cycles, using the clock enable will result in latency twice higher because SQRT is not operational every second cycle...
interesting.
thanks
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Basically yes though there are some unique exceptions e.g. you can use another clock to sample data without having to stop the register in which case some edge(before sampling edge) will be violated but the sampling edge will be ok. The main point is to realise that the fitter will "look" at your multicycled path and apply deconstraint on latching register + apply full freedom to push data transition off launch register within MC periods.
The data stream sequence will stay correct but may shift relative to sampling edge from the single MC default where you assume transition occurs within one clock period.
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