timequest alt_sqrt how to choose properly signals for multicycle

Yes, I've completely forgotten of timequest cookbook, where similar case is described. i'm not sure however, whether I fully understand your claim:

"multicycle would not apply unless you have designed to sample every two clocks by whatever way"

what is it? the way I see this multicycle thingy is, that even if one clocks a register on, say 160MHz, if you shift data into such register on 40MHz, the 40MHz timing constraints should apply, right?

let's imagine two registers, which are clocked by 160MHz clock, but the actual rate on the data pin is 40MHz, hence data change once per 25ns while clock is 6.25ns. Now, if in between those two registers I have a combinatorial logic, which takes 15ns to propagate, is this valid for multicycle? This is kind of my problem. I do not use clock enable to 'freeze' the clock. I'm using fast clock, but with slow data...