Altera_Forum
Honored Contributor
Honored ContributorTime Constraints issue
Hi everyone,
I got some problems when I used the TimeQuest to constraint the time. In my design, a 100M source frequency come into the FPGA and two 200M frequency get out by the FPGA PLL. One for the A/D clock, another for the D/A clock. I edit a SDC file to constraint the timing because the timing analyzer in the quartus reports a amount of setup time error. After that, there is not any errors in the timing report. But the D/A output don’t tally with the A/D input. What result in this situation however there has a correct timing report. Does It means my cell timing is good and the probability reason is the I/O timing??? set_input_delay -clock { adc_clk_ext } -min 1.0 [get_ports {AD_IN [*]}] set_input_delay -clock { adc_clk_ext } -max 3.0 [get_ports {AD_IN [*]}] set_output_delay -clock { dac_clk_ext } -min -0.5 [get_ports {DA_OUT [*]}] set_output_delay -clock { dac_clk_ext } -max 1.5 [get_ports {DA_OUT [*]}] PS: As the multicycle decides the step time relationship and my data_arrive_time is 7.9ns, I set the multicycle 2 to change the step time relationship to 10ns for the data_arrive time. My question is can I set up the multicycle much bigger to change the step time relationship to 15ns,20ns,25ns…etc so that the time becomes more easier to be matched. It seems the bigger the better, is that right? set_multicycle_path -from [get_clocks {usys_pll|altpll_component|auto_generated|pll1|clk[2]}] -to [get_clocks {usys_pll|altpll_component|auto_generated|pll1|clk[2]}] -setup -start 2 set_multicycle_path -from [get_clocks {usys_pll|altpll_component|auto_generated|pll1|clk[2]}] -to [get_clocks {usys_pll|altpll_component|auto_generated|pll1|clk[2]}] -hold -start 1 Clock name Type Period Frequency adc_clk_ext Virtual 5.000 200.0 MHz ady Base 10.000 100.0 MHz clk100M Base 10.000 100.0 MHz dac_clk_ext Virtual 5.000 200.0 MHz usys_pll|altpll_component|auto_generated|pll1|clk[0] Generated 5.000 200.0 MHz usys_pll|altpll_component|auto_generated|pll1|clk[1] Generated 40.000 25.0 MHz usys_pll|altpll_component|auto_generated|pll1|clk[2] Generated 5.000 200.0 MHz
