Occasional ContributorThe written code works fine, but the behavior is wrong.
Hello,
This is the code for the clock that displays minutes/seconds, and attaches the project folder.
The written code works fine, but the first digit of the second position becomes '4' upon reset.
That is, 04,05,06,07,08,09 -> 10,11,12,13,14,15,16,17,18,19 -> 20,21,22,23, was expected.
The problem works as 14,15,16,17,18,19 -> 24,25,26,27,28,29 -> 34,35....
I have a question.
There is nothing wrong with the code in the Verilog HDL editor,
Is there a place where I write code that can affect the behavior in other areas that are not visible to me?
For example,
Is there a place to write scripts?
Is there a place to write the header file?
Is it possible to insert hidden characters in the editor?
I wonder if code can be injected during compilation, etc.?
If possible, what can I do to prevent this problem?
Because, I feel like someone is tampering with my PC's Quartus from a remote location.
thank you.
Quartus 20.1.1 (image attached)
FPGA: M10, 10M08SCU169, 50MHz Clock
BOARD: QMTECH_MAX10_10M08SCU169
Coding Purpose: For Minute/Second Clock
Peripheral: 74HC595 Built-in 7-segment LED (with schematic image attached)
