The warning about pll

The PLL's have dedicated output ports called PLL_CLKOUT. If you take a PLL clock and drive it directly to one of these ports, it will bypass the global clock tree and go directly out, resulting in the least amount of jitter and the warning should go away.

That being said, I have never heard of a clock that didn't work by not going out a regular I/O. A good example is source-synchronous interfaces that transmit the clock with the data. Those work by having the clock go out a regular I/O instead of the PLL_CLKOUT(so the clock and data delays match), and can pass data extremely high rates(say 800Mbps+). The 533MHz DDRs, whose data rate is twice that, does not use the PLL_CLKOUT.

My point is that, if you're just using it to create an off chip clock, the PLL_CLKOUT is great, but I think the warning is often interpreted too severely, as many, many designs use regular I/O to send clocks out without problem.