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Altera_Forum's avatar
Altera_Forum
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12 years ago

The virtual clock about input or output in timing constrain

When we do timing constrain in input or output, usually we need create a virtual clock. My question is, how can I know the phase relation between virtual clock and clock inside the system, in order t...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Possibly. Let's say clk1 drives some external device and clk2 drives the FPGA, and external device drives the FPGA. Let's also say the board oscillator takes 1ns longer to drive the external device. Also say the external device has a Tco of 4.7 and min Tco of 2.4, and drives onto ports din[*] of the FPGA. You might do something like:

create_clock -period 10.0 -waveform {1.0 6.0} -name ext_clk

create_clock -period 10.0 -name fpga_sys_clk [get_ports fpga_sys_clk]

set_output_delay -clock ext_clk -max 4.7 [get_ports {din[*]}]

set_output_delay -clock ext_clk -min 2.4 [get_ports {din[*]}]