Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

The virtual clock about input or output in timing constrain

When we do timing constrain in input or output, usually we need create a virtual clock. My question is, how can I know the phase relation between virtual clock and clock inside the system, in order t...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

--- Quote Start ---

If you don't want that, use the -waveform option to do something different, like:

create_clock -period 10.0 -waveform {1.0 6.} This is a clock with a rising edge at 1 and falling at 6, i.e. shifted 1ns in time.

--- Quote End ---

Will there be a case that I will create two clocks as:

create_clock clk1 -period 10.0 -waveform {1.0 6.0}

create_clock clk2 -period 10.0 -waveform {0 5.0}

??

Thanks.