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Altera_Forum's avatar
Altera_Forum
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12 years ago

The virtual clock about input or output in timing constrain

When we do timing constrain in input or output, usually we need create a virtual clock. My question is, how can I know the phase relation between virtual clock and clock inside the system, in order t...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Yes. Whenever you do:

create_clock -period Xns

TQ assumes the rising edge is at 0ns and the falling edge is at X/2ns. If you don't want that, use the -waveform option to do something different, like:

create_clock -period 10.0 -waveform {1.0 6.}

This is a clock with a rising edge at 1 and falling at 6, i.e. shifted 1ns in time.