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The virtual clock is "perfect" so it rises at 0, 10, etc. The clock going into the FPGA is also perfect at that point, but inside the FPGA will have different delays to everything it drives, which TQ accounts for. I guess yes, they rise at 0 without any PLL shifts(or something in your .sdc to say you've shifted it externally). THe .sdc describes the ideal clocks, and then the place-and-route does stuff to those clocks which are part of the timing analysis, but you don't have to know what those delays are up front or do anything to account for them. (Which would be very chicken-and-egg-y, since you would need to know the place-and-route to enter the .sdc constraints, but don't want to do place-and-route until the .sdc is correct...)
If I'm not answering your question, please put more detail on what you want it to account for, or maybe a more detailed example?
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Thanks, Rsyc. I think you answered my question. But let me double check to confirm it. So when I create a clock outside the FPGA, it maybe:
1. system clock to drive inner logic, input or outputs
2. virtual clock to drive external components
In both cases, the clock will rise at 0. Does my understanding right?
Thanks.
Honored Contributor
