The virtual clock about input or output in timing constrain

The virtual clock is "perfect" so it rises at 0, 10, etc. The clock going into the FPGA is also perfect at that point, but inside the FPGA will have different delays to everything it drives, which TQ accounts for. I guess yes, they rise at 0 without any PLL shifts(or something in your .sdc to say you've shifted it externally). THe .sdc describes the ideal clocks, and then the place-and-route does stuff to those clocks which are part of the timing analysis, but you don't have to know what those delays are up front or do anything to account for them. (Which would be very chicken-and-egg-y, since you would need to know the place-and-route to enter the .sdc constraints, but don't want to do place-and-route until the .sdc is correct...)