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Altera_Forum
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12 years ago

The virtual clock about input or output in timing constrain

When we do timing constrain in input or output, usually we need create a virtual clock. My question is, how can I know the phase relation between virtual clock and clock inside the system, in order t...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Thanks, Rysc.

I think my statement is unclear which confused you. So you mentioned this: "For example, if your virtual clock driving an input has a 10ns period with a rise at 0". Actually, my question is here, for the clocks which drive the input and output respectively, how can I know when they rise? E.g., assume both of them has a 10ns period, but how can I know when they rise between 0 and 10？ Do we always assume they rise at 0 if we don't do any specific design in oscillations?

Thanks very much.