The question about signal propagate in trace or cable

Thanks, Alex.

Yes, I just take the " hundred metres" as an example, I know we need a lot of other things if we really need trasmitt signals in that long distance. I think nobody will transmit parallel data in that long distance.

For case 1, your answer is This won't cause timing issues. Then I think there is an interesting case inside FPGA.

Assume If I have a very long path inside the FPGA, that the signal propagating that path needs more than one clock cycle (assume it arrives the destination FF before 2nd flip-flop). But this is just initial delay, the later data still arrives destination FF cycle by cycle. If I made my design in the destination FF to work as this delay, then my design should work, there should be no timing issue in my design, right?

Definitely, I need proper timing constrain in sdc file to make Quratus II STA to understand my timing to avoid timing failure problem.

Thanks.