The problem for using DPA PLL

In your SerDes , have you used the DPA clocks in them? To do so, you need to do the following:

1. In the PLL config tun on the “Enable access to the PLL DPA output” option . The “phout” output port will be produced. The phout port is 8 bits wide. You need to re-generate PLL with Netlist option enabled after modifying.

2. In your project directory, delete the ALTLVDS_RX .v file, then rename the ALTLVDS_RX_syn.v file to ALTLVDS_RX.v

3. Manually edit the ALTLVDS_RX .v to make all occurances of the “rx_dpaclock” port 8 bits wide

4. In your design, connect the PLL “phout” output to the ALTLVDS_RX “rx_dpaclock” input