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Insert an ALTCLKCTRL megafunction in the clock path between the dedicated clock input pin and the Altera_PLL. Note, using a global primitive or global signal assignment for the clock signal is not sufficient, the ALTCLKCTRL megafunction must be instantiated in your design.
This is not necessary when the clock input pin has dedicated access to the Altera_PLL.
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the PLL output will connect to non-DPA serdes, if i add one clkctrl between input and PLL, the quartus will show error message:
pll which drives at least one non-DPA-mode SERDES, must be driven by a dedicated input
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