The need for error correction codes

I think, the basic danger of inexpected behaviour with the design is outside the CPLD, clock input and signal output. The design itself is simple and rather slow clocked. It's not easy to cause an error here.

The above safe state machine suggestion is important regarding the possibility, that the clock may be affected by interferences. A non safe state machine may get stuck to an illegal state and never recover due to a single glitch in the input clock.

Safe transmission of output signals is mainly a question of appropriate wiring.