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For instance, the "Fast model clock hold" minimum slack is only 0.397 ns. I am running a 20 MHz clock. Is this acceptable?
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You can use a setting to add clock uncertainty for things like clock jitter (for a PLL in non-MAX II devices and for your clock input in your design) that the Quartus timing analysis does not cover by default. Unless I'm forgetting something, clock uncertainty is all you need in order to count on even a zero slack (anything not negative) being good enough for internal timing for a global clock with no logic in the clock path.
You might want to have some positive slack for I/O timing unless you are sure that your I/O timing constraints account for all uncertainties for what is happening outside the FPGA (like needing to wait a little longer for a noisy signal to settle out).
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