The need for error correction codes

I haven't heard of anyone doing error correction internal to programmable logic other than for soft errors (single event upset) caused by external radiation. Device families like Stratix III have built-in error detection for that. I expect that MAX II has an extremely low probability of this kind of error.

Your bigger risk will be from anything that does not follow proper design practices.

Be sure that you have full constrained the timing and run the timing analysis with both slow and fast models.

Be extra careful with anything asynchronous in the design. If you are using asynchronous resets, run recovery and removal analysis or make certain that your design does not need this analysis. If you have more than one clock (sounds like you probably don't), be extra careful crossing between clock domains. Don't have any logic in your clock path (don't use any ripple or gated clocks). Run the Design Assistant to see whether it finds any potential problems.