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MinzhiWang's avatar
MinzhiWang
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

The interconnection between ADC and Cyclone10GX FPGA

Hello Guys, I have posted several threads to ask several questions about new FPGAs for us, which is Cyclone 10 GX FPGA. The latest one is https://community.intel.com/t5/Programmable-Devices/How-to-r...
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FvM's avatar
FvM
Icon for Super Contributor rankSuper Contributor
2 years ago

Hi,
you need dedicated inputs for clocks driving a PLL, for SERDES reference clocks specifically a dedicated input in the same bank.


Clocks not driving a PLL must not necessarily use dedicated inputs, but achieve better performance (lower jitter and skew) if they do.

The actual answer depends on your ADC sync scheme and timing margin.