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Altera_Forum
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18 years ago

The efficiency of DDR and DDR2 SDRAM High-Performance Controller

Hi, everyone! Have anybody used Altera's DDR and DDR2 SDRAM High-Performance Controller in Cyclone 3?What do you think of the efficiency of this controller? I think the efficiency won't b...
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Altera_Forum
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18 years ago

What Avalon master are you using to test this? Is it a custom master logic or Altera's?

Be aware that the Nios processor master is not fully latency aware, at least in my tests (if you are using a Nios to test this).

A DMA type master with proper latency aware logic will achieve 100% same-row efficiency, in between consecutive refreshes of course.