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MinzhiWang's avatar
MinzhiWang
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2 months ago

The DC_FIFO issue of Cyclone 10 GX devices

Hello Guys, We are using 10CX220F780 and 10CX105F780 devices now. They are communicating thru XCVR. So one DC_FIFO is realized between RX received data and user logic fabric.   This DC FIFO operat...
Core Logic
dandanlau's avatar
dandanlau
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1 month ago

Hi,

I assume this works in simulation so it's not reproducible there?

What happens if you delay the first (or subsequent) wrreq by a couple of cycles so the data is stable first, would you still see the same issue?

MinzhiWang's avatar
MinzhiWang
Icon for Occasional Contributor rankOccasional Contributor
1 month ago

Hi dandanlau,

Yes, I did that you said already. I applied one or two or three cycles delay for wrreq. But the issue still there.