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MinzhiWang's avatar
MinzhiWang
Icon for Occasional Contributor rankOccasional Contributor
16 days ago

The DC_FIFO issue of Cyclone 10 GX devices

Hello Guys, We are using 10CX220F780 and 10CX105F780 devices now. They are communicating thru XCVR. So one DC_FIFO is realized between RX received data and user logic fabric.   This DC FIFO operat...
Core Logic
MinzhiWang's avatar
MinzhiWang
Icon for Occasional Contributor rankOccasional Contributor
14 days ago

Hi Ash,

Thanks for you reply.

I think this issue doesn't relate with power-up issue. For our board has been powered on for long time when we want to operate FIFO. We have one look up table required to send to object FPGA from top-level thru DAQ and tranceiver. So you can see from previous SignalTap II images. The FIFO writing time interval is about 100 ns (Actually, our DAQ speed is only 10MHz.), and our system clock frequency is 100MHz. This look up table can be written correctly after this issue. This problem only happens when power-up/download new program. It means that we have to write this look up table two times, because the first time has this problem. We can't repeat this issue after it appears one time. If we want to repeat this issue, we have to power-up again, or download program again.

I apply 'rdreq' with '1' just for verifying FIFO writing operation. Our normal 'rdreq' signal is generated as you mentioned.

 

BTW, we don't open 'aclr' port for FIFO. And I don't think we can check 'wrclk' from signaltap, for sgnaltap clock frequency is equal to 'wrclk'.

 

Best Regrad

Ash_R_Altera's avatar
Ash_R_Altera
Icon for Regular Contributor rankRegular Contributor
10 days ago

Hi,

May I know which Quartus version is being used? Please share a smaller version of your design to replicate the issue on our side. Simulatable design is preferred.

Parallely on your side, I would like to see the DC_FIFO ports in the signal tap. Please add as many signals at the FIFO level, including 'aclr' to the signal tap and send us a screen shot. Additionally add XCVR rx_ready signal as well.

 

I didn't quite understood what you mean by "we don't open 'aclr' port". Do you mean you never assert and de-assert the 'aclr' port? Please clarify.

 

Regards,

Altera Tech Support

  • MinzhiWang's avatar
    MinzhiWang
    Icon for Occasional Contributor rankOccasional Contributor
    10 days ago

    Hi Ash,

    1. My Quartus Prime Pro version is 23.4.0.79.

       

    2.  We don't use 'aclr' port. As following image indicate

       

      Maybe, I can enable 'aclr' and use it for verification.
  • Ash_R_Altera's avatar
    Ash_R_Altera
    Icon for Regular Contributor rankRegular Contributor
    10 days ago

    Also, let us know all the FIFO IP settings that you have used.

     

    Regards,

    Altera Tech Support