The DC_FIFO issue of Cyclone 10 GX devices

Hi Minzhi,

Thank you for providing the detailed description and waveforms. I assume that the FIFO is configured to Normal mode.

This behavior typically occurs due to transceiver clock instability during power-up/reset or premature read requests before pointer synchronization is complete.

Probable root cause & recommendations:

1. Transceiver Clock Stability & Reset Sequencing (`rx_ready`):
  - At power-up/reconfiguration, the transceiver CDR and PLL calibrate, during which `rx_clkout` can experience glitches or unstable frequencies before locking.
  - Ensure the DCFIFO `aclr` (asynchronous reset) is held asserted until the Transceiver PHY Reset Controller asserts `rx_ready` (and both `wrclk` and `rdclk` are stable).
  - After `aclr` is deasserted, wait at least 3 to 5 clock cycles before asserting `wrreq`.

2. Read Request (`rdreq`) Gating:
  - Do not tie `rdreq` permanently high (`1'b1`). Asserting `rdreq` while `rdempty` is high causes FIFO underflow:
    - In Normal Mode: Reading while empty results in invalid/zero data.
  - Always qualify your read logic: only assert `rdreq` when `rdempty == 1'b0`.

3. Is it possible to bring the DC_FIFO signals 'aclr' and 'wrclk' also in the signal tap?

For more details on reset sequencing and timing requirements, please refer to the FIFO Intel FPGA IP User Guide on Altera.com.

Best regards,
Altera Applications Support