Forum Discussion
ContributorThe cyclone v soc GIC interrupt priority issues
Hi,
Please check this below API function, you can also directly set the LEVEL or EDGE triggered.
ALT_STATUS_CODE alt_int_dist_trigger_set(ALT_INT_INTERRUPT_t int_id,
ALT_INT_TRIGGER_t trigger_type)
{
// See GIC 1.0, section 4.3.12.
if ((uint32_t)int_id >= ALT_INT_PROVISION_INT_COUNT)
{
return ALT_E_BAD_ARG;
}
else if ((alt_int_flag[int_id] & INT_FLAG_IMPLEMENTED) == 0)
{
return ALT_E_BAD_ARG;
}
else if (int_id < 16)
{
if ( (trigger_type == ALT_INT_TRIGGER_AUTODETECT)
|| (trigger_type == ALT_INT_TRIGGER_SOFTWARE))
{
return ALT_E_SUCCESS;
}
else
{
return ALT_E_BAD_ARG;
}
}
else
{
uint32_t regoffset = int_id >> 4;
uint32_t regbitshift = ((int_id & 0x0F) * 2) + 1;
if (trigger_type == ALT_INT_TRIGGER_AUTODETECT)
{
if (int_id <= 32) { trigger_type = ALT_INT_TRIGGER_EDGE; } // PPI
else if (int_id <= 40) { trigger_type = ALT_INT_TRIGGER_EDGE; } // CPU0_PARITYFAIL
else if (int_id <= 47) { trigger_type = ALT_INT_TRIGGER_LEVEL; } // CPU0_DEFLAGS
else if (int_id <= 56) { trigger_type = ALT_INT_TRIGGER_EDGE; } // CPU1_PARITYFAIL
else if (int_id <= 63) { trigger_type = ALT_INT_TRIGGER_LEVEL; } // CPU1_DEFLAGS
else if (int_id <= 66) { trigger_type = ALT_INT_TRIGGER_EDGE; } // SCU
else if (int_id <= 69) { trigger_type = ALT_INT_TRIGGER_EDGE; } // L2_ECC
else if (int_id <= 70) { trigger_type = ALT_INT_TRIGGER_LEVEL; } // L2 (other)
else if (int_id <= 71) { trigger_type = ALT_INT_TRIGGER_LEVEL; } // DDR
else if (int_id <= 135) { /* do nothing */ } // FPGA, !!!
else { trigger_type = ALT_INT_TRIGGER_LEVEL; } // everything else
}
switch (trigger_type)
{
case ALT_INT_TRIGGER_LEVEL:
alt_clrbits_word(alt_int_base_dist + 0xC00 + regoffset * sizeof(uint32_t), 1 << regbitshift); // icdicfrn
break;
case ALT_INT_TRIGGER_EDGE:
alt_setbits_word(alt_int_base_dist + 0xC00 + regoffset * sizeof(uint32_t), 1 << regbitshift); // icdicfrn
break;
default:
return ALT_E_BAD_ARG;
}
return ALT_E_SUCCESS;
}
}
"Did you suggest I test the time form the isr signal send to GIC to the interrupt callback function called". Yes in C code only can write piece of code for timer before ISR start and end.
Regards
Tiwari
Frequent ContributorHi,
FPGA to HPS interrupts can be used as edge or level trigger and their GIC interrupt number is from 72 to 135.
You need to keep the signal set until the ISR is not executed, at the end of ISR execution you can reset the signal.
You can use the API to set the interrupt trigger type from the #include "alt_interrupt.c".
alt_int_dist_trigger_set(ALT_INT_INTERRUPT_GPIO2, ALT_INT_TRIGGER_AUTODETECT);
Regards
Tiwari
CAlexHi
"You need to keep the signal set until the ISR is not executed, at the end of ISR execution you can reset the signal."
I want to avoid that if possible. The tasks are very time related, so I want to use edge trigger and let the signal auto reset in case other ISR block the tunnel. Do you know how long the ISR needs to be set ? Or how to calculate the presice time pluse needed?
"alt_int_dist_trigger_set(ALT_INT_INTERRUPT_GPIO2, ALT_INT_TRIGGER_AUTODETECT);"
For this case, the FPGA ISR cant be set to AUTODETECT. You must choose EDGE or LEVEL trigger.
I hope this can help others.
Thank you
