the clock divider with enable using verilog

Hi,

yes indeed, every FF is to be clocked by the 50MHz as usual but every FF meant to run at 1MHz needs the enable signal as well. This enable signal in a good compiler should be wired up to the enable port of the FF.The compiler infers that from the location of the signal construct(not its name!, you may even insert your construct directly instead of explicit signal).

There are also certain pitfalls when using enable. In particular be careful about the logic level of any signal when enable is inactive, you may have to freeze it or deactivate it depending on the design.

It is well-known that cascaded enable in multi-module systems is prone to bugs and needs extra care.

But overall, it is excellent from timing perspective, though some may argue that it means more power.

Kaz