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Hi,
To answer the question, there is no easy way to write a BIST that will test every bit of circuitry you plan to exercise in a design every time you power up. Sorry!
- Paul
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Actually, this is fairly common in high-reliability ASIC designs. There are tools out there (Like Mentor's L-BIST) that will take your design, add the ability to control and observe the design's nodes and give you something like a processor interface for driving the tests. I think these tools could be used on an FPGA design as well, but I think you loose structural control through the FPGA's mapping process, so you end up with something that's more like a functional BIST rather than a structural BIST - the difference being that failures map to structural elements which may not be controllable/observable from the functional test.
I guess what I'm saying is that you can instrument your design so that it's self-checking and get yourself most of the way to a good test at the cost of additional logic utilization. There are tools out there to help you with this. However, you don't get he same level of BIST capability as you would in an ASIC design because you can't insert a test point at every structural node in an FPGA ALM, for example.
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