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Altera_Forum
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18 years ago

Testing of internal resources

Does anyone have a simple code set for testing internal FPGA resources to aide in creating a BIST type test methodology. Something like a LUT based Pattern generator, the block to be tested (LU...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

While customer being always right is true, the first step is teaching the customer about the matters he/she should be concerned about. FPGAs are not like RAM chips which get exercised at 100% (theoretically) during the normal operation of the product.

Once you synthesize and route/fit an FPGA design, it will stay in place (using the same LEs) during the lifetime of the product, or until you recompile the design. If you need BIST, implement it into your design, the same way you would do when designing an ASIC. Testing the unused LEs does not make much sense.