Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

Testing of internal resources

Does anyone have a simple code set for testing internal FPGA resources to aide in creating a BIST type test methodology. Something like a LUT based Pattern generator, the block to be tested (LU...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

Paul,

What if you have a requirement to run a BIST on every power-up? It's not uncommon in high-reliability applications - especially ones with very long service lives.

As for an answer to the original question, I wonder if it would be possible to somehow use the SEU error detection (CRC_Error) circuitry as part of a device test.