testbench integer type

Dear all,

Below is my testbench code that i simulate in ModelSim.

---------------------------------------------------------------------

library IEEE;

use IEEE.Std_logic_1164.all;

use IEEE.Numeric_Std.all;

entity reg_tb is

end;

architecture bench of reg_tb is

component reg

PORT (

input : IN integer RANGE -127 TO 127;

clk : IN bit;

output : OUT integer RANGE -127 TO 127

);

end component;

signal input: integer RANGE -127 TO 127;

signal clk: bit;

signal output: integer RANGE -127 TO 127 ;

constant clock_period: time := 10 ns;

signal stop_the_clock: boolean;

begin

uut: reg port map ( input => input,

clk => clk,

output => output );

stimulus: process

begin

-- Put initialisation code here

input <= "3";

clk <= "0";

wait for 100ns;

input <= "12";

clk <= "1";

wait for 100ns;

stop_the_clock <= true;

wait;

end process;

clocking: process

begin

while not stop_the_clock loop

clk <= '0', '1' after clock_period / 2;

wait for clock_period;

end loop;

wait;

end process;

end;

This is the error:

Error (10515): VHDL type mismatch error at reg_tb.vhd(35): integer type does not match string literal

Can anyone tell me, where I'm wrong..Many thanks