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Altera_Forum's avatar
Altera_Forum
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15 years ago

Systemverilog packed structs in Quartus II?

I have a systemverilog header file (types.svh) that contains a number of the following:

typedef struct packed {

bit [127:0] field1;

bit [63:0] field2;

bit [127:0] field3;

bit [63:0] field4;

} name_of_struct;

When I try to synthsize it in a file:

`include "types.svh"

module mod_name(i_port, ...)

input name_of_struct i_port;

Quartus II just dumps out a bunch of errors saying "Verilog HDL error: object "name_of_struct" is not declared. It's like QuartusII isn't actually seeing my `include file or something. Any suggestions? The console window doesn't generate any output as if the `include is actually being evaluated, so I'm not sure what's going on.

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    this feature may not be supported by Quartus II yet. i don't use System Verilog, can you paste the typedef into your actual source HDL and see if Quartus recognizes it that way?

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    Hmm. So copying the typedef into my module appears to work:

    `include "types.svh"

    module mod_name(i_port, ...)

    typedef struct packed {

    bit [127:0] field1;

    bit [63:0] field2;

    bit [127:0] field3;

    bit [63:0] field4;

    } name_of_struct;

    input name_of_struct i_port;

    Does Quartus II really not support `including files with common declarations? That seems like such a basic feature.