SystemVerilog for Verification

Hello, I want to know how popular SystemVerilog for Verification is in the FPGA development community. I've looked into using Assertions and find them very usefull. I've also read a few books by Spear on Verification. When trying to implement some of the things Spear mentions in his book "SystemVerilog for Verification" such as Classes, FIFOs, Queues, Randomizers, etc. requires simulators that are very expensive. Implementing Assertions is not too costly and easier for managers to fund rather than shelling out $15K+ on simulators that are SV Verification capable.

Being new at Verification and not able to try it out to see its pros or cons, I would like to ask the Forum how popular is SV for Verification? Is Assertions sufficient for most things in development? I would rather ask the Forum these questions before asking my manager to shell out $15K for a simulator cable of SV for Verification and then find out that I rarely use all of its features to justify the cost. Asking my manager to shell out $8K for an Assertion cablable simuator is different than asking $15K for a simulator that support SV for Verification.

Thanks,

joe