SystemVerilog code

Hi there,

Why I assign the value i to out.len is 0. It should give me 4.

module SVerilog(input clock, reset);

typedef struct {

int len;

} packet_t;

function int init(

output packet_t out,

input int l);

out.len = l;

return 0;

endfunction

function int add(

output packet_t out,

input int a,

input int b);

int i, y;

i = a + b;

i = out.len; // It should give me i = 4 instead 0

y = a + b;

out.len = y;

return 0;

endfunction

packet_t out;

reg [31:0] a;

reg [31:0] b;

int x;

initial begin

a = 5;

b = 10;

x = init(out, 4);

x = add(out, a, b);

# 10 $display("a = %d, b = %d, out.x = %d", a, b, out.len);

end

endmodule