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Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

system verilog

Hi,

Trying to use the code below:

module portlist_localparam# (

parameter aPARAM = 1,

localparam aLOCAL = 2

)

endmodule

Get error: Error (10170): Verilog HDL syntax error at portlist_localparam.sv(4) near text "localparam"; expecting an identifier ("localparam" is a reserved keyword )

is that a valid error? how to solve for system verilog?

Thanks in advance,

Best regards

Angel

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    The parameter list of a Verilog or systemVerilog module only accept "parameter".

    So just replace "localparam" with "parameter"