System Verilog for Carry Save Array Multiplier (Proble!!!)

hi,

I was trying to design a 4x4 carry save array multiplier, i use a system verilog code to infer the full adders array, there were no code errors and i used the RTL view to verify the connections, everything looks fine, but i got weird results (e.g. 3x1 = 15; 7 *1 = 17 !!! ) :confused:...

my aim is to make the code expandable to any bit width:(...

can any give advise????

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//Carry_Save_Array_Mult0.sv

module Carry_Save_Array_Mult0(

a,

b,

p

);

parameter DATA_WIDTH = 4;

input [(DATA_WIDTH - 1):0]a;

input [(DATA_WIDTH - 1):0]b;

output [((DATA_WIDTH*2) - 1):0]p; // the product

wire s[(DATA_WIDTH - 1):0][(DATA_WIDTH - 1):0]; // partial product array

wire ci1[(DATA_WIDTH - 1):0][(DATA_WIDTH - 1):0]; // carry_in wires array

wire co1[(DATA_WIDTH - 1):0][(DATA_WIDTH - 1):0]; // carry_out wires array

wire [3:0]w0 = ({a[0],a[0],a[0],a[0]})&(b[3:0]);

wire [3:0]w1 = ({a[1],a[1],a[1],a[1]})&(b[3:0]);

/*********************************************************************************************************/

//this process is used to generate the first row of the multiplier

genvar i;

generate

for(i = 0; i < DATA_WIDTH ; i++)

begin: first_row

FULL_ADDER fa_r0( // call the full_adder module

.x(w0[i+1]),

.y(w1),

.ci(co1[0][i-1]),

.co(co1[0]),

.p(s[0][i])

);

end

endgenerate

/**********************************************************************************************/

// this process is used to generate the rest of the rows by instantiating the full adders

genvar j, k;

generate

for(k = 1; k < (DATA_WIDTH - 1) ; k++)

begin: rest

for(j = 0; j < DATA_WIDTH ; j++)

begin: of_the_rows

if(j < (DATA_WIDTH - 1)) begin

FULL_ADDER fa_r1( // call the full_adder module

.x(a[k+1]&b[j]),

.y(s[k-1][j]),

.ci(co1[k][j-1]),

.co(co1[k][j]),

.p(s[k][j])

); end

else begin

FULL_ADDER fa_r1(

.x(a[k+1]&b[j]),

.y(co1[k-1][j]),

.ci(co1[k][j-1]),

.co(co1[k][j]),

.p(s[k][j])

); end

end // first for loop

end // second for loop

endgenerate

wire p0 = a[0]&b[0]; // bit[0] of the result

assign p = {co1[2][3],s[2][3],s[2][2],s[2][1],s[2][0],s[1][0],s[0][0],p0}; // result[7:1]

endmodule

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//FULL_ADDER.v

module FULL_ADDER(

x,

y,

ci,

co,

p

);

input x, y, ci;

output co, p;

wire a = x^y;

wire b = x&y;

wire c = ci&a;

assign p = ci^a;

assign co = b|c;

endmodule

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Regards.