Forum Discussion
Altera_Forum
Honored Contributor
16 years agoI used your method of debugging by attaching to the processor whilst it was running. From this I found that my spi core had its SSO bit in the control register asserted when loaded from the epcs device. When debugging this bit is randomly cleared at startup, which enables the spi to work. I changed my spi intialisation code to clear this bit at startup and everything works fine. Having this bit set somehow disables the spi from doing anything, which is not what it is supposed to do. The SSO bit is supposed to permanantly set the slave select bits that are selected in the slave select register. This doesn't make very much sense. However the problem has been removed but without satisfactory understanding.
If you can help with an explanation feel free. If you have better things to do (like me) don't worry about it. Thanks for your help, much appreciated!!