system runs whilst debugging but not on its own

All right, this is a little complicated. If you set the reset address of the processor to onchip memory, it will boot out of the onchip memory. If you set the reset address of the processor to the EPCS device, it will boot out of the EPCS device (which uses the boot loader you mentioned) but run out of whatever memory you've specificed in your system library project (sounds like onchip memory to me). If you are truly running in onchip memory, there is no need for you to boot from the EPCS flash because your processor code will actually be compiled into the FPGA image.

One thing I would double-check though is that you have enough onchip memory to support your software.

Anyway here is what you should be doing:

1 - Make sure the processor's reset address to onchip memory. Regenerate your SoPC system if necessary.

2 - Compile your software project.

3 - Compile your Quartus project. It is essential that this be done after you compile your software project or the software code will not be compiled into the fpga image.

4 - Program your EPCS flash with your firmware image (using either JIC method or nios2-flash-programmer).

Another thing you can try after the FPGA boots and the processor is running is to use the NIOS2 IDE to attach to the processor without re-downloading the code, then you can try and debug and see what is going on.

Jake