Honored Contributor
Honored ContributorHey Dave
i measured bit period on signal tap to be around 52us. thats 104us period... 9600 baud same baud rate from putty->signaltap (rx) and nios->signaltap (tx) this is with putty set to 24000 and the qsys uart set at 9600. i did email ftdi and they want me to update drivers. Ill do that tomorrow. i put the 50MHz clock into signal tap as well and it looks like it has correct period If qsys thinks its got a 50MHz clock and generates a 9600 baud off that, and that 9600 is closer to 24000, then that would mean the 50MHz clock is 125MHz. Ill double check the board and system builder. well, look at this straight from terasic manual... Table 3-6 Clock Source, Signal Name, Default Frequency, Pin Assignments and Functions Source Schematic Signal Name Default Frequency I/O Standard Cyclone V GX Pin Number Application U20 CLOCK_125_p 125.0 MHz LVDS PIN_U12 U20 CLOCK_125_n 125.0 MHz LVDS PIN_V12 X2 CLOCK_50_B5B 50.0 MHz 3.3-V PIN_R20 CLOCK_50_B6A 50.0 MHz 3.3-V PIN_N20 U20 CLOCK_50_B7A 50.0 MHz 2.5-V PIN_H12 U20 CLOCK_50_B8A 50.0 MHz 2.5-V PIN_M10 U20 REFCLK_p0 125.0 MHz 1.5-V PCML PIN_V6 U20 REFCLK_n0 125.0 MHz 1.5-V PCML PIN_W6 U20 REFCLK_p1 156.25 MHz1.5-V PCML PIN_N7 U20 REFCLK_n1 156.25 MHz1.5-V PCML PIN_P6 So my top level .v does use CLOCK_125_p. I seem to remember doing that from a "my first nios" tutorial. To use a 50MHz clock instead of that 125MHz, is it as simple as replacing CLOCK_125_p in my top level instantiation with say CLOCK_50_B5B? Will the FPGA know to just jump over and use that pin as my clock? See, i told you im very green... thanks Dave! im learning a lot
