Forum Discussion
Altera_Forum
Honored Contributor
11 years agoHi Dave
Yes, i triggered on the RX pin and typed in putty and got what i wanted. and had nios printf ABC and saw that show up in putty. so it works. im just not sure about why it works at 24000... The clock rate for my system is 50MHz. I read that UART core manual and see that the divisor can be read at UARTBaseAddr + 4... heres my uart settings as described in system.h # define ALT_MODULE_CLASS_uart_0 altera_avalon_uart # define UART_0_BASE 0x20020800 # define UART_0_BAUD 9600 # define UART_0_DATA_BITS 8 # define UART_0_FIXED_BAUD 0 # define UART_0_FREQ 50000000 # define UART_0_IRQ 2 # define UART_0_IRQ_INTERRUPT_CONTROLLER_ID 0 # define UART_0_NAME "/dev/uart_0" # define UART_0_PARITY 'N' # define UART_0_SIM_CHAR_STREAM "" # define UART_0_SIM_TRUE_BAUD 0 # define UART_0_SPAN 32 # define UART_0_STOP_BITS 1 # define UART_0_SYNC_REG_DEPTH 2 # define UART_0_TYPE "altera_avalon_uart" # define UART_0_USE_CTS_RTS 0 # define UART_0_USE_EOP_REGISTER 0 So if i read the uart divisor reg in system console, i get master_read_memory $master 0x20020800 10 0x41 0x00 0x00 0x00 0x43 0x00 0x00 0x00 0x60 0x00 x43 is my divisor?? If thats the case, then applying the equations in the uart core handbook: baudrate = clkfrq/(divisor + 1) and divisor =int (clk_freq/baudrate +.5) my baudrate should be 50e6/(d67+1) = 735Kbaud??? or calculating the theoretical divisor... 50e6/24000 +.5 = d2084 = x824 So something is not correct or my understanding is wrong Im going to try regenerating everything from scratch to see if that makes any difference Any thoughts? thanks