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This is what i have Cyclone V GX Starter Kit
http://www.terasic.com.tw/cgi-bin/page/archive.pl?language=english&no=830 --- Quote End ---
Ok, thanks.
Note that this kit has an FTDI FT232R USB-to-UART device. Unfortunately the device is not an FTDI USB-to-FIFO device which are faster, however, according to the FT232R data sheet, the UART can be operated at 1Mbaud or perhaps 3MBaud. You can use this interface to communicate with your NIOS II processor, rather than using the JTAG port. Leave the JTAG port for use by SignalTap II and SystemConsole (if you even need to use SystemConsole - the NIOS II processor should be sufficient).
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I have a DUT that communicates via SPI protocol. We need a host interface to this to send the SPI command words (65K+ 32bit words) and collect the response from the DUT and transfer back to host PC for processing
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So why use an FPGA? An FTDI cable or a microcontroller can be used to do this?
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What i have done so far:
qsys generated SPI core that works perfectly with our DUT. I can implement a subset of commands and the DUT responds correctly.
small nios c program to format the instructions to spi and save response from DUT and store into 32bit words
i have used the master_read_to_file over system console to read back these 32bit words back to host, analyze in matlab and it looks correct.
i can use the master_write_from_file over system console to write my memory but it does interfere with the current nios mem polling/triggering, same goes for the master_write_memory
What i need to do is take this small scale subset and scale up to met full transfer to/from DUT.
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Ok.
I would recommend changing over to using the USB-to-UART to transfer the data directly to the NIOS II processor. I have not used the Qsys UART core, so have no idea of how good the performance is. However, you do have an FPGA, so even if the UART does not meet your requirements, you can easily write an interface that does.
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So i need to move 65K+ (or more) 32bit instructions to memory (every once in a while, the instructions may change. so this process can be slower, but not snail pace)
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Using the USB-to-UART this will take 65 x 1024 x 32b / 1Mbaud = 2.1 seconds. Is that fast enough?
The USB-to-UART devices are much faster, as is the MPSSE mode, so you could always use the GPIO connectors if you needed a faster transfer rate.
Given that you are using a development kit, I'd argue that you just "use what you've got", and improve that interface on any final design you implement if you decide you need a faster transfer rate.
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I liked your master_write_memory suggestion vs master_write_32. that sped things up to be around 10 seconds. this is acceptable
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In that case, 2 seconds would be a further improvement :)
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the SPI transfer to DUT must be decently fast.
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That is totally dependent on your signal integrity. If you're using the GPIO pins to communicate with your DUT, then you'll need to check the SPI signals for signal integrity using a scope.
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This SPI transfer will happen multiple times per test based on changing test conditions. So i envision nios code running in a loop and being triggered by the host after test conditions are set up.
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I don't see a need to trigger the NIOS II processor. If you consider the NIOS II processor your "server" and it listens on its serial port, then you send it a command to update the SPI data, followed by the 65K x 32-bit samples. The processor can then initiate a new test, or if you like, you can have another command to start the test. Since the board has memory, you could use the UART to send multiple test vectors to memory, and then have the NIOS II select and use one of the test vectors.
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I'm open to suggestions. id rather learn to do this stuff correctly the first time than try to replicate bad design after bad design
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Let me know what you think of the above suggestions.
Cheers,
Dave
Honored Contributor
