Forum Discussion
Altera_Forum
Honored Contributor
11 years agoIf you open your Qsys system, the default page with your component connections will also have your memory map. If the addresses on the right-side of the GUI are all visible, eg., registers at 0000_0000h, ram at 1000_0000h, then the address map of both masters is identical. It is possible to make the masters have different address maps, but then the addresses on the default page get replaced with something like <multiple>.
What devices do you have in your Qsys memory map, eg., a NIOS II processor and the default JTAG master that comes as part of the memory controller, or did you explicitly include a JTAG-to-Avalon-MM master bridge? Cheers, Dave